6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

3D stacking and computational imaging are two major driving forces for CMOS image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with sensor circuits while leveraging advanced CMOS technologies including FinFET. To accommodate this trend, we need to design blocks such as comparators, readouts, transmitters, and PLLs, using digital architectures in logic processes with a minimum number of resistors and capacitors. Achieving 100% array-to-chip area ratio is an ultimate goal of 3D CIS. For this reason, all peripheral circuits must be under the pixel array. However, row and column circuits may overlap at the corner if both pitches are equal to pixel pitch. To avoid this issue, we make row and pixel pitch the same, and shrink column pitch to 82% to spread the column signal to array width using the “river routing” tools introduced for display-driver ICs, as shown in Fig. 6.8.1. The 3D stacking technology we apply [1] is top-metal face-to-face, and it can put 3D connections under a backside-illuminated pixel array. Therefore it increases array-to-chip area ratio comparing with a TSV chip that uses area outside the pixel array. This chip demonstrates the 3D connections at the center of the uniform 33Mpixel array and seamless image readout using 4 identical 8.3Mpixel circuit units. Instead of developing new circuitry, we can combine 16 compact units for 133Mpixel at the same frame rate and save the extra driving power.