A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications

Random linear network coding (RLNC) is an emerging coding technique, which can provide several advantages in wireless networks, such as throughput gains, increased data robustness, and better utilization of network resources. In this paper, we present the first custom VLSI implementation of RLNC, integrated with an ultralow-power 2.4-GHz transmitter. We examine its energy efficiency and error recovery performance in the context of Internet of Things applications, and we perform experiments quantifying its benefits when it operates separately and jointly with physical layer forward error correction (FEC) codes, as a joint channel and network coding scheme. The chip is fabricated in a 65-nm CMOS process, occupies <inline-formula> <tex-math notation="LaTeX">$2 \times 1.3 ~{\mathrm{ m}}{\mathrm{ m}}^{2}$ </tex-math></inline-formula> and consumes 580 pJ/bit for processing and transmitting data at 1 Mbps. The digital packet processor and encoder occupies <inline-formula> <tex-math notation="LaTeX">$200\times 200 ~\mu {\mathrm{ m}}^{2}$ </tex-math></inline-formula>, consists of an on-chip memory, a multi-rate convolutional encoder, and a RLNC accelerator with configurable redundancy, and consumes <inline-formula> <tex-math notation="LaTeX">$15\mu \text{W}$ </tex-math></inline-formula>, operating at 0.4 V. For improved spectral efficiency, an on-chip pulse shaping filter is implemented, reducing side lobes by 28 dB while consuming <inline-formula> <tex-math notation="LaTeX">$15\mu \text{W}$ </tex-math></inline-formula>. According to our over-the-air experiments, RLNC can provide an effective SNR improvement of 5.6 dB when combined with FEC rate 1/2, and 3.4 dB without FEC, at a packet error rate of <inline-formula> <tex-math notation="LaTeX">$10^{-2}$ </tex-math></inline-formula>.