First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is veri...

[1]  Michael J. Krasowski,et al.  Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation , 2011 .

[2]  Michael J. Krasowski,et al.  Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect , 2016 .

[3]  Michael J. Krasowski,et al.  SiC JFET Integrated Circuits for Extreme Environment Electronics , 2012 .

[4]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[5]  D. Schroder.  Semiconductor Material and Device Characterization , 1990 .

[6]  Charles Scozzie,et al.  Modeling the temperature response of 4H silicon carbide junction field-effect transistors , 1997 .

[7]  Glenn M. Beheim,et al.  Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect , 2016 .

[8]  P. Neudeck,et al.  High-temperature electronics - a role for wide bandgap semiconductors? , 2002, Proc. IEEE.

[9]  Glenn Beheim,et al.  6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C , 2008 .

[10]  Paul K. Chu,et al.  Processing and Characterization , 2013 .

[11]  Paolo Antognetti,et al.  Semiconductor Device Modeling with Spice , 1988 .

[12]  John D. Cressler,et al.  Extreme Environment Electronics , 2012 .

[13]  J. Palmour,et al.  Conductivity Anisotropy in Epitaxial 6H and 4H Sic , 1994 .

[14]  R. Pierret.  Field effect devices , 1983 .

[15]  Glenn Beheim,et al.  Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package , 2016 .

[16]  Glenn Beheim,et al.  Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits , 2016 .

[17]  Glenn M. Beheim,et al.  Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect , 2016, IEEE Electron Device Letters.

[18]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[19]  Liang-Yu Chen,et al.  Stable Electrical Operation of 6H–SiC JFETs and ICs for Thousands of Hours at 500 $^{\circ}\hbox{C}$ , 2008, IEEE Electron Device Letters.

[20]  Philip G. Neudeck,et al.  Experimental and Theoretical Study of 4H-SiC JFET Threshold Voltage Body Bias Effect from 25 °C to 500 °C , 2016 .