Reliability and integration of ultra-thin gate dielectrics for advanced CMOS

Abstract The rapid scaling of CMOS technology over the last few years has resulted in the reduction of gate dielectric thickness to only a few nanometers. Some estimates suggest that standard SiO 2 (or its nitrogen containing variants) will cease to useful when thickness are reduced to between 1.0–2.0 nm. The major causes for concern, assuming that such thin dielectrics may be grown reliably with any reasonable yield, seem to centered upon either process integration issues, (for example boron penetration), or upon the increasing gate leakage which lead to questions regarding dielectric integrity and reliability or to standby power consumption. The future of CMOS down to and below the 0.1 μm gate lengths may well hinge on finding a replacement of silicon dioxide as the gate insulator. However, even for 2.0–4.0 nm dielectrics currently being used for the development of 0.1 – 0.25 μm technologies. There is only limited understanding of the issues pertaining to the reliability of the gate dielectric.