A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three stages, a current-reuse technique is employed in the current mode multiplying digital-to-analog converters (MDACs). An operational transconductance amplifier (OTA) converts an input voltage into current; A current-steering DAC reuses the OTA bias current. The OTA and the DAC generate the sub-ADC residue in a current domain. As a result, both power consumption and thermal noise for the MDAC are reduced. A transimpedance amplifier (TIA) with a feedback resistor is utilized to convert the current signal to a voltage residue signal for the next stage. An off-chip calibration scheme is used to correct interstage gain and nonlinearity errors. The fabricated ADC achieves 68.1 dB signal-to-noise-and-distortion ratio (SNDR) and 82.3 dB spurious free dynamic range (SFDR) for a sinusoidal input at 4.17 MHz. The ADC operates at a maximum sampling frequency of 260 MHz. With an input signal at 123.129 MHz, the measured SNDR/SFDR are 66.3/78.22 dB, respectively. The total power consumption for the ADC running at maximum speed is 15.38 mW. Thus, the pipeline ADC achieves a 167.4 dB figure-of-merit (FoM). The chip was manufactured in a TSMC 40-nm CMOS process.