CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation.<<ETX>>

[1]  A. Abidi,et al.  A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS , 1989 .

[2]  W. Freeman,et al.  How brains make chaos in order to make sense of the world , 1987, Behavioral and Brain Sciences.

[3]  K. Aihara,et al.  Neural networks and chaos , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[4]  K. Aihara,et al.  Chaotic neural networks , 1990 .

[5]  John B. Hughes,et al.  Switched current filters , 1990 .

[6]  M. Inoue,et al.  A chaos neuro-computer , 1991 .

[7]  E. Vittoz MOS transistors operated in the lateral bipolar mode and their application in CMOS technology , 1983, IEEE Journal of Solid-State Circuits.

[8]  K. Aihara,et al.  Chaos and phase locking in normal squid axons , 1987 .

[9]  D. L. Birx,et al.  Chaotic oscillators and complex mapping feed forward networks (CMFFNs) for signal detection in noisy environments , 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.