Template Vertical Dictionary-Based Program Compression Scheme on the TTA

As a critical technology in the embedded system nowadays, program code compression can improve the code density and reduce the power consumption. Especially for the Transport Triggered Architecture (TTA), the long instruction word is one of the key problems to degrade the processor performance. In this paper, with the analysis to the spatial locality of the data transports, a template vertical dictionary-based program compression scheme is proposed. It not only efficiently eliminates the redundant empty slots as well as the invalid long immediate encodings, but also applies the vertical dictionarybased compression at the slot level. The experiment shows that this scheme achieves the compression ratio of 32.3%, especially corresponds to the tiny dictionary size. Then, the effects on area and power consumption are also measured. The total area of the processor core and the local instruction memory could be reduced by about 29% and power consumption by nearly 25% respectively.