Route-on-Fly: A single cycle router

Network-on-Chip (NoC) architecture provides a platform for inter-core communication in a multicore system. In this work we propose a single cycle minimally buffered Route-on-Fly (RoF) router that uses the link traversal time of the data packet to perform route calculations. We also propose a 2 cycle variant of the Route-on-Fly (RoF) router in this paper. 4 × 4 NoC meshes built using proposed architectures and the baseline router have been synthesized on 28nm Xilinx Kintex7 KC705 FPGA to assess for implementability. We show that the proposed single cycle minimally buffered Route-on-Fly router based NoC occupies 94% less memory cells and 30% less router latency than the baseline router synthesized. A detailed performance analysis shows that even in the best case of single link contention, the proposed Route-on-Fly NoC outperforms the bufferless NoC by about 20% and the baseline NoC by about 75%.

[1]  Fernando Moraes,et al.  Evaluation of Routing Algorithms on Mesh Based NoCs , 2004 .

[2]  John Kim,et al.  Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[3]  Sudhakar Yalamanchili,et al.  Centralized buffer router: A low latency, low power router for high radix NOCs , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[4]  Simon W. Moore,et al.  Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[5]  John Jose,et al.  Minimally buffered single-cycle deflection router , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Minxuan Zhang,et al.  The design and implementation of two-cycle NoC router , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[7]  Hamid Sarbazi-Azad,et al.  An energy-efficient virtual channel power-gating mechanism for on-chip networks , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  John Kim,et al.  Router microarchitecture and scalability of ring topology in on-chip networks , 2009, 2009 2nd International Workshop on Network on Chip Architectures.

[9]  William J. Dally.  Virtual-channel flow control , 1990, ISCA '90.

[10]  Chita R. Das,et al.  ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[11]  Li-Shiuan Peh,et al.  Single-cycle collective communication over a shared network fabric , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[12]  Onur Mutlu,et al.  A case for bufferless routing in on-chip networks , 2009, ISCA '09.

[13]  Oliver Chiu-sing Choy,et al.  A low-latency NoC router with lookahead bypass , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[14]  Shigeru Oyanagi,et al.  The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers , 2010, 2010 First International Conference on Networking and Computing.

[15]  Tsutomu Yoshinaga,et al.  Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors , 2011, IEEE Transactions on Computers.

[16]  Kevin Kai-Wei Chang,et al.  MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[17]  Hideharu Amano,et al.  Prediction router: Yet another low latency on-chip router architecture , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[18]  Chrysostomos Nicopoulos,et al.  ElastiStore: An elastic buffer architecture for Network-on-Chip routers , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).