Class-based weighted fair queuing scheduling on quad-priority Delta Networks

Contemporary networks support multiple priorities, aiming to differentiate the quality of service (QoS) levels offered to individual traffic classes. Support for multiple priorities necessitates the introduction of a scheduling algorithm, to select each time the next packet to transmit over the data link. Class-based weighted fair queuing (CBWFQ) scheduling and its variations are widely used as a scheduling technique since it is easy to implement and prevent the low-priority queues from starvation, i.e. receiving no service during periods of high-priority traffic. CBWFQ effectively thus offers low-priority queues, the opportunity to transmit packets even though the high-priority queues are not empty. In this paper, we present the modelling and performance evaluation of a single-buffered, four-priority multistage interconnection network (MIN) operating under the CBWFQ scheduling policy. Performance evaluation is conducted through simulation, and the performance metrics obtained can be used by MIN designers to set the appropriate queue weights according to the expected traffic and the desired QoS levels for each priority class, delivering efficient thus systems.

[1]  G. E. Rizos,et al.  Routing and Performance Evaluation of Dual Priority Delta Networks under Hotspot Environment , 2009, 2009 First International Conference on Advances in Future Internet.

[2]  Dietmar Tutsch,et al.  Multilayer multistage interconnection networks , 2003 .

[3]  Euripidis Glavas,et al.  Routing and Performance Analysis of Double-Buffered Omega Networks Supporting Multi-class Priority Traffic , 2008, 2008 Third International Conference on Systems and Networks Communications.

[4]  Eleftherios Stergiou,et al.  Performance evaluation for multistage interconnection networks servicing unicast and multicast traffic (by partial operation) , 2009, 2009 International Symposium on Performance Evaluation of Computer & Telecommunication Systems.

[5]  George Varghese,et al.  Efficient fair queueing using deficit round robin , 1995, SIGCOMM '95.

[6]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[7]  Euripidis Glavas,et al.  Performance Evaluation of Two-Priority Network Schema for Single-Buffered Delta Networks , 2007, 2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications.

[8]  Josep Torrellas,et al.  The performance of the cedar multistage switching network , 1997, Supercomputing '94.

[9]  Ian F. Akyildiz,et al.  Wireless mesh networks: a survey , 2005, Comput. Networks.

[10]  Toshio Soumiya,et al.  The large capacity ATM backbone switch "FETEX-150 ESP" , 1999, Comput. Networks.

[11]  G. Jack Lipovski,et al.  Banyan networks for partitioning multiprocessor systems , 1998, ISCA '98.

[12]  Hee Yong Youn,et al.  Performance analysis of finite buffered multistage interconnection networks , 1992, Proceedings Supercomputing '92.

[13]  Scott Shenker,et al.  Analysis and simulation of a fair queueing algorithm , 1989, SIGCOMM '89.

[14]  Martin J. Fischer,et al.  Approximation for a two-class weighted fair queueing discipline , 2010, Perform. Evaluation.

[15]  Israel Cidon,et al.  Two priority buffered multistage interconnection networks , 2004, 2004 Workshop on High Performance Switching and Routing, 2004. HPSR..

[16]  Sung-Chun Kim,et al.  Hierarchical multistage interconnection network for shared-memory multiprocessor system , 1997, SAC '97.

[17]  José Duato,et al.  Efficient Deadline-Based QoS Algorithms for High-Performance Networks , 2008, IEEE Transactions on Computers.

[18]  W. Richard Stevens,et al.  TCP/IP Illustrated, Volume 1: The Protocols , 1994 .

[19]  Erwin P. Rathgeb,et al.  Performance analysis of buffered Banyan networks , 1991, IEEE Trans. Commun..

[20]  G. Chuanxiong SRR: An O(1) time complexity packet scheduler for flows in multi-service packet networks , 2001, SIGCOMM '01.

[21]  Xin Li,et al.  Architectures of Internet Switches and Routers , 2007 .

[22]  Sidnie Feit,et al.  Local Area High Speed Networks , 2000 .

[23]  Hung-Hsiang Jonathan Chao,et al.  Next generation routers , 2002, Proc. IEEE.

[24]  H. T. Mouftah,et al.  Survey of ATM Switch Architectures , 1995, Comput. Networks ISDN Syst..

[25]  William E. Weihl,et al.  Lottery scheduling: flexible proportional-share resource management , 1994, OSDI '94.

[26]  Costas Vassilakis,et al.  Performance Analysis of blocking Banyan Switches , 2007 .

[27]  Euripidis Glavas,et al.  Modelling and performance evaluation of a novel internal-priority routing scheme for finite-buffered multistage interconnection networks , 2011, Int. J. Parallel Emergent Distributed Syst..

[28]  Janak H. Patel,et al.  Processor-memory interconnections for multiprocessors , 1979, ISCA '79.

[29]  Jung-Yoon Kim,et al.  Analytical modeling of a Multistage Interconnection Network with Buffered a×a Switches under Hot-spot Environment , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[30]  S. Kumar,et al.  Mathematical Modelling and Simulation of a Buffered Fault Tolerant Double Tree Network , 2007, 15th International Conference on Advanced Computing and Communications (ADCOM 2007).

[31]  Masayoshi Nabeshima Packet-Based Scheduling for ATM Networks Based on Comparing a Packet-Based Queue and a Virtual Queue , 1999 .

[32]  Marion Kee,et al.  Analysis , 2004, Machine Translation.

[33]  Costas Vassilakis,et al.  Improving Performance of Finite-Buffered Blocking Delta Networks with 2-Class Priority Routing through Asymmetric-Sized Buffer Queues , 2008, 2008 Fourth Advanced International Conference on Telecommunications.

[34]  Lixia Zhang VirtualClock: A New Traffic Control Algorithm for Packet-Switched Networks , 1991, ACM Trans. Comput. Syst..

[35]  Debasis Mitra,et al.  Design of generalized processor sharing schedulers which statistically multiplex heterogeneous QoS classes , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[36]  Jörg Liebeherr,et al.  Workconserving vs. non-workconserving packet scheduling: an issue revisited , 1999, 1999 Seventh International Workshop on Quality of Service. IWQoS'99. (Cat. No.98EX354).

[37]  Nick McKeown,et al.  On the speedup required for combined input- and output-queued switching , 1999, Autom..

[38]  Mohamed Othman,et al.  The Development of Crosstalk-Free Scheduling Algorithms for Routing in Optical Multistage Interconnection Networks , 2010 .

[39]  Iwao Sasase,et al.  Multistage Interconnection Multicast ATM Switch with Exclusive Routes for Delay-Sensitive and Loss-Sensitive Cells , 1999 .

[40]  Chuanxiong Guo,et al.  SRR: an O(1) time-complexity packet scheduler for flows in multiservice packet networks , 2004, IEEE/ACM Transactions on Networking.

[41]  S. Jamaloddin Golestani,et al.  A self-clocked fair queueing scheme for broadband applications , 1994, Proceedings of INFOCOM '94 Conference on Computer Communications.

[42]  Howard Jay Siegel,et al.  The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems , 1982, IEEE Transactions on Computers.

[43]  Paul G. Spirakis,et al.  An Analytical Performance Model for Multistage Interconnection Networks with Finite, Infinite and Zero Length Buffers , 1998, Perform. Evaluation.

[44]  Costas Vassilakis,et al.  Performance Study of Multilayered Multistage Interconnection Networks under Hotspot Traffic Conditions , 2010, J. Comput. Networks Commun..

[45]  Debasis Mitra,et al.  Analysis, approximations and admission control of a multi-service multiplexing system with priorities , 1995, Proceedings of INFOCOM'95.

[46]  Gheith A. Abandah,et al.  Modeling the communication performance of the IBM SP2 , 1996, Proceedings of International Conference on Parallel Processing.

[47]  I. Damgård,et al.  The protocols. , 1989, The New Zealand nursing journal. Kai tiaki.

[48]  Elizabeth Suet Hing Tse Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router , 2004, J. Syst. Archit..

[49]  David L. Black,et al.  Definition of the Differentiated Services Field (DS Field) in the IPv4 and IPv6 Headers , 1998, RFC.

[50]  Thomas G. Robertazzi Performance Analysis of a Packet Switch Based on SingleBuffered Banyan Network , 1993 .

[51]  Luis Orozco-Barbosa,et al.  Switching Modules for ATM Switching Systems and Their Interconnection Networks , 1993, Comput. Networks ISDN Syst..

[52]  Yih-Chyun Jenq,et al.  Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network , 1983, IEEE J. Sel. Areas Commun..

[53]  José Duato,et al.  A New Cost-Effective Technique for QoS Support in Clusters , 2007, IEEE Transactions on Parallel and Distributed Systems.

[54]  Leonard Kleinrock,et al.  Performance analysis of finite-buffered multistage interconnection networks with a general traffic pattern , 1991, SIGMETRICS '91.

[55]  Mehrnaz Moudi,et al.  A Challenge for Routing Algorithms in Optical Multistage Interconnection Networks , 2011 .