Modeling and design of asynchronous circuits

This technology review explores the behavioral and structural design domains for asynchronous circuits and systems. It proceeds bottom up, introducing relevant concepts, terminology and techniques through a succession of simple examples. There are seven main points: 1) Signal transitions provide a key to understanding the switching behavior of asynchronous logic. 2) Burst-mode circuits and speed-independent control circuits offer reliable operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding schemes are suitable for representing data because they address the issues of data validity and completion detection. 5) Asynchronous networks, constructed from modules and channels, provide a systems architecture for asynchronous design. 6) Handshaking on channels, which controls data communication and synchronization between modules, is implemented using signal transitions. 7) The translation of algorithmic descriptions into asynchronous networks facilitates an automated approach to large-scale system design.

[1]  L. S. Nielsen,et al.  Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid , 1999, Proc. IEEE.

[2]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[3]  Marly Roncken Defect-oriented testability for asynchronous ICs , 1999 .

[4]  Supratik Chakraborty,et al.  Min-max timing analysis and an application to asynchronous circuits , 1999, Proc. IEEE.

[5]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[6]  Ivan E. Sutherland,et al.  Two FIFO ring performance experiments , 1999, Proc. IEEE.

[7]  Victor I. Varshavsky,et al.  Self-Timed Control of Concurrent Processes , 1989 .

[8]  M. B. Josephs,et al.  An overview of D-I algebra , 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

[9]  Erik Brunvand,et al.  Translating concurrent programs into delay-insensitive circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Kenneth S. Stevens,et al.  Automatic Synthesis of Fast Compact Self-Timed Control Circuits , 1993 .

[11]  Steven M. Nowick,et al.  An introduction to asynchronous circuit design , 1998 .

[12]  Jim D. Garside,et al.  AMULET2e: an asynchronous embedded controller , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[13]  Paul Day,et al.  Four-phase micropipeline latch control circuits , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Peter A. Beerel,et al.  Automatic gate-level synthesis of speed-independent circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[15]  Bill Lin,et al.  Symbolic hazard-free minimization and encoding of asynchronous finite state machines , 1995, ICCAD.

[16]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[17]  Eby G. Friedman,et al.  System Timing , 2000, The VLSI Handbook.

[18]  P. Marston,et al.  Designing asynchronous standby circuits for a low-power pager , 1999 .

[19]  David L. Dill,et al.  Synthesis of Asynchronous Controllers for Heterogeneous Systems , 1994 .

[20]  Niraj K. Jha,et al.  MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines , 1999 .

[21]  Luciano Lavagno,et al.  Logic decomposition of speed-independent circuits , 1999 .

[22]  Willem C. Mallon,et al.  Building finite automata from DI specifications , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[23]  Kenneth Y. Yun Automatic synthesis of extended burst-mode circuits using generalized C-elements , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[24]  Mark B. Josephs,et al.  CMOS design of the tree arbiter element , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[25]  Steven M. Nowick,et al.  An implicit method for hazard-free two-level logic minimization , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[26]  Ganesh Gopalakrishnan,et al.  Application-specific programmable control for high-performance asynchronous circuits , 1999 .

[27]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[28]  Paul I. Pénzes,et al.  The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[29]  Kenneth Y. Yun,et al.  Average-case optimized transistor-level technology mapping of extended burst-mode circuits , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[30]  Wesley A. Clark Macromodular computer systems , 1967, AFIPS '67 (Spring).

[31]  Alain J. Martin The limitations to delay-insensitivity in asynchronous circuits , 1990 .

[32]  Kees van Berkel Beware the isochronic fork , 1992, Integr..

[33]  Makoto Iwata,et al.  DDMPs: self-timed super-pipelined data-driven multimedia processors , 1999 .

[34]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[35]  S. H. Unger A building block approach to unlocked systems , 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

[36]  Ganesh Gopalakrishnan,et al.  A technique for synthesizing distributed burst-mode circuits , 1996, DAC '96.

[37]  Luciano Lavagno,et al.  Complete state encoding based on the theory of regions , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[38]  Alain J. Martin Asynchronous datapaths and the design of an asynchronous adder , 1992, Formal Methods Syst. Des..

[39]  Ad M. G. Peeters,et al.  Single-rail handshake circuits , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[40]  J. Ebergen,et al.  Response-time properties of linear asynchronous pipelines , 1999 .

[41]  Alain J. Martin Programming in VLSI: from communicating processes to delay-insensitive circuits , 1991 .

[42]  Bill Lin,et al.  Symbolic hazard-free minimization and encoding of asynchronous finite state machines , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[43]  David E. Muller Asynchronous logics and application to information processing , 1962 .

[44]  David L. Dill,et al.  Synthesis of asynchronous state machines using a local clock , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.