Resource allocation and binding approach for low leakage power

We propose a leakage power minimization approach based on multi-threshold CMOS (MTCMOS) technology. A clique partitioning-based resource allocation and binding algorithm is presented, which maximizes the idle periods of modules in the data-path. Modules with significant idle times are selectively bound to MTCMOS instances. We developed a parameterizable MTCMOS component library, characterized with respect to sleep transistor width. Using this characterization, the leakage power-delay trade-off is analyzed and optimal sleep transistor widths are identified. For three well known HLS benchmarks, we obtain an average leakage power reduction of 22.44%. The main disadvantage of MTCMOS technology is performance degradation. We present a performance recovery technique based on multi-cycling and introduction of slack. With this technique, the performance penalty reduces to as low as 14.28%. We obtain an average leakage power reduction of 17.46% after performance recovery. The average area overhead incurred due to the introduction of MTCMOS modules is 10.21%. Results are presented for 0.18 /spl mu/m CMOS technology.

[1]  Zhanping Chen,et al.  Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[2]  Kaushik Roy.  Leakage power reduction in low-voltage CMOS designs , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[3]  Niraj K. Jha,et al.  Leakage power analysis and reduction during behavioral synthesis , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Farid N. Najm,et al.  A gate-level leakage power reduction method for ultra-low-power CMOS circuits , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[5]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[6]  Srinivas Katkoori,et al.  Behavioral synthesis of datapaths with low leakage power , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[7]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[8]  Daniel P. Siewiorek,et al.  Facet: A Procedure for the Automated Synthesis of Digital Systems , 1983, 20th Design Automation Conference Proceedings.

[9]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[10]  C. Chakrabarti,et al.  Architectural approaches to reduce leakage energy in caches , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[11]  K. Roy,et al.  DRG-cache: a data retention gated-ground cache for low power , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[12]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.