Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger

This work investigates the suitability of using an FPGA coprocessor for speedup track finding algorithm for ATLAS Level 2 trigger. Two realizations of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64Bit/66MHz PCI bus, 1024 Mb DDR RAM main memories with Red Hat Linux 7.1; and hybrid C++ and VHDL realization tested on the same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim). In the TRT-LUT algorithm, the most time consuming parts were implemented in VHDL and using the FPGA coprocessor. This realization can give us speed-up by factor ~2 for hybrid FPGA/CPU realization in comparison with CPU-only implementation.