A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC‘16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

[1]  Matteo Sonza Reorda,et al.  Test of Reconfigurable Modules in Scan Networks , 2018, IEEE Transactions on Computers.

[2]  Matteo Sonza Reorda,et al.  A suite of IEEE 1687 benchmark networks , 2016, 2016 IEEE International Test Conference (ITC).

[3]  Hans-Joachim Wunderlich,et al.  Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation , 2015, TODE.

[4]  Bernd Becker,et al.  Formal verification of secure reconfigurable scan network infrastructure , 2016, 2016 21th IEEE European Test Symposium (ETS).

[5]  Matteo Sonza Reorda,et al.  Test Time Minimization in Reconfigurable Scan Networks , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

[6]  Irith Pomeranz,et al.  On the Detectability of Scan Chain Internal Faults An Industrial Case Study , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[7]  Melvin A. Breuer,et al.  A universal test sequence for CMOS scan registers , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[8]  Chi W. Yau,et al.  An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[9]  Matteo Sonza Reorda,et al.  On the testability of IEEE 1687 networks , 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

[10]  Farrokh Ghani Zadegan,et al.  Design automation for IEEE P1687 , 2011, 2011 Design, Automation & Test in Europe.

[11]  Luigi San Paolo.  New techniques for reducing the duration of reconfigurable scan network test , 2018 .

[12]  Edward J. McCluskey,et al.  ATPG for scan chain latches and flip-flops , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[13]  Giovanni Squillero,et al.  A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks , 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

[14]  Hans-Joachim Wunderlich,et al.  Structure-Oriented Test of Reconfigurable Scan Networks , 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

[15]  Melvin A. Breuer,et al.  Reconfigurable scan chains: a novel approach to reduce test application time , 1993, ICCAD.