Accurate Nano-Circuits Reliability Evaluations Based on Combining Numerical Simulations with Monte Carlo

This paper proposes a new approach to accurately evaluate the reliability of future nano-circuits. The proposed approach combines the accuracy and intuitiveness of Monte Carlo (MC) simulation with the simplicity and high modeling capacity of numerical simulations. This approach is important and timely as the expected size of future nano-circuits will make the exclusive usage of MC simulation timely prohibitive. At the same time, simulation methods that depend solely on numerical simulations are unfortunately not accurate enough. Experimental results show that the circuit reliability calculated by the proposed approach is very close to the reliability calculated based on MC simulation only.

[1]  J. Meindl,et al.  Limits on silicon nanoelectronics for terascale integration. , 2001, Science.

[2]  M. Forshaw,et al.  Architectures for reliable computing with unreliable nanodevices , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[3]  Valeriu Beiu,et al.  What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details , 2007, IWANN.

[4]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[5]  Claude E. Shannon,et al.  Reliable Circuits Using Less Reliable Relays , 1956 .

[6]  Siegfried Selberherr,et al.  SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jianbo Gao,et al.  Faults, error bounds and reliability of nanoelectronic circuits , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[8]  Marta Z. Kwiatkowska,et al.  PRISM: Probabilistic Symbolic Model Checker , 2002, Computer Performance Evaluation / TOOLS.

[9]  V. Beiu,et al.  On the Reliability of Four Full Adder Cells , 2007, 2007 Innovations in Information Technologies (IIT).

[10]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[11]  V. Beiu,et al.  On the Reliability of Majority Gates Full Adders , 2008, IEEE Transactions on Nanotechnology.

[12]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[13]  V. Beiu,et al.  Design and analysis of SET circuits: using MATLAB modules and SIMON , 2004, 4th IEEE Conference on Nanotechnology, 2004..

[14]  Christof M Niemeyer,et al.  Rational design of DNA nanoarchitectures. , 2006, Angewandte Chemie.

[15]  Finn V. Jensen,et al.  Bayesian Networks and Decision Graphs , 2001, Statistics for Engineering and Information Science.

[16]  Valeriu Beiu.  A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov , 2004 .

[17]  Valeriu Beiu,et al.  Gate Failures Effectively Shape Multiplexing , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[18]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[19]  V. Beiu,et al.  A fresh look at majority multiplexing when devices get into the picture , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).

[20]  Bonnie A. Sheriff,et al.  A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre , 2007, Nature.

[21]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[22]  Sandeep K. Shukla,et al.  Reliability Analysis of Large Circuits Using Scalable Techniques and Tools , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Valeriu Beiu,et al.  Serial Addition: Locally Connected Architectures , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.