论文信息 - A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n

A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n

This paper presents a 3.9-to-5.39GHz all-digital fractional-N PLL for WiMax/WLAN 11n application. The ADPLL uses a self-corrected TDC to achieve meta-stable-error-free operation, wide dynamic range and high timing resolution in a small chip area. The rms jitter from 1kHz to 40MHz is 320fs at 4.51GHz while the calibrated bandwidth is 300KHz. With aid of the fast temperature tracking loop, the operational temperature range is extended to from −40 to 120oC. The loop settling time is 32us.

Hsiang-Hui Chang | Chia-Huang Fu | Monty Chiu

[1] Matthew Z. Straayer,et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[2] Ping-Ying Wang,et al. A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3] K. Muhammad,et al. All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[4] A. Abidi,et al. A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue , 2007, 2007 IEEE Symposium on VLSI Circuits.

[5] Matthew Z. Straayer,et al. A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.