Hot-Carrier Injection Degradation in Advanced CMOS Nodes: A Bottom-Up Approach to Circuit and System Reliability

The development of most applications in the microelectronics industry is driven by an increase in the working frequency. Each product can be used under various types of mission profiles, thus forcing a large variety of signal types on each transistor. One growing concern involves the capability to guarantee the working frequency not only of a fresh product, but after years of operation. As a consequence, accurately characterizing the reliability at a transistor level became mandatory, with the necessity to consider various stress conditions and the obligation to achieve a good prediction capability. In this context, the degradation of the transistor under hot-carrier injection (HCI) degradation stress can no longer be studied at the so-called worst-case stress condition [1] but must cover all V gs/V ds working conditions [2]. The study of new stress conditions has evidenced new degradation phenomena [such as electron–electron scattering (EES) or multiple vibrational excitation (MVE)]. Their nontrivial understanding [2–4] requires analyzing the degradation at a microscopic scale in order to come up with predictive modeling at a transistor level and even higher hierarchical modeling levels.