Nowadays, Dynamic Partial Reconfiguration of digital circuits like Field-Programmable Gate Arrays (FPGA) appears as a sustainable hardware evolution phenomenon. Like many other architectures, Cellular Nonlinear Networks (CNN) are able to be adjusted or reprogrammed, when the characteristics of the problem are changed. Currently, changing memory content like parameters effects only the operation of architecture which has all functions, including momentarily redundant ones. The appeared question is how the overhead created by functional redundancy of hardware can be decreased. As discussed and studied in this paper, hardware pieces can be reconfigured to completely different designs when the characteristic of the problem is changed in run-time. The paper aims to exhibit the benefits of Dynamic Partial Reconfiguration feature of contemporary FPGAs on CNNs varying/evolving in time under the Network of Networks concept. For this purpose, trigger-wave generating subnetworks are combined using different reconfigurable partitions of an FPGA and a primary network is constituted which generates different trigger-wave patterns. This conceptual design unrolls how dynamic partial reconfiguration is capable to realize irregular/asymmetric network components.
[1]
Z. Voroshazi,et al.
FPGA based emulated-digital CNN-UM implementation with GAPU
,
2008,
2008 11th International Workshop on Cellular Neural Networks and Their Applications.
[2]
Tamás Roska,et al.
The CNN universal machine: an analogic array computer
,
1993
.
[3]
Barry Wellman,et al.
Community: from neighborhood to network
,
2005,
CACM.
[4]
Mark E. J. Newman,et al.
The Structure and Function of Complex Networks
,
2003,
SIAM Rev..
[5]
Mustak E. Yalcin,et al.
A 16 × 16 Cellular Logical Network with partial reconfiguration feature
,
2014,
2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA).
[6]
Ling Guan,et al.
A network of networks processing model for image regularization
,
1997,
IEEE Trans. Neural Networks.
[7]
Ramazan Yeniceri,et al.
Hybrid processor population for odor processing
,
2012,
2012 IEEE International Symposium on Circuits and Systems.
[8]
Turhan Karadeniz.
Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric
,
2010
.