Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils × 410 mils of silicon area.