Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 μm double-poly CMOS technology. The quiescent power consumption is only 80 μW using a dual supply voltage of ± 1.35 V The S&H occupies 0.075 mm 2 of silicon area.