False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
暂无分享,去创建一个
Jing-Jia Liou | Kwang-Ting Cheng | A. Krstic | L.-C. Wang | K. Cheng | J. Liou | Li-C. Wang | A. Krstic
[1] Kwang-Ting Cheng,et al. Fast statistical timing analysis by probabilistic event propagation , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[2] Sudhakar M. Reddy,et al. Long and short covering edges in combination logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] David R. Tryon,et al. Statistical Failure Analysis of System Timing , 1984, IBM J. Res. Dev..
[4] Seiichiro Tani,et al. Efficient path selection for delay testing based on partial path evaluation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[5] Kwang-Ting Cheng,et al. Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[6] Sharad Malik,et al. Statistical timing analysis of combinational logic circuits , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[7] David Hung-Chang Du,et al. Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[8] Katsumi Homma,et al. Pre-layout delay calculation specification for CMOS ASIC libraries , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[9] Robert K. Brayton,et al. Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network , 1989, 26th ACM/IEEE Design Automation Conference.