A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

This article presents a 5-GS/s 12-b passive-sampling <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula>-interleaved hybrid analog-to-digital converter (ADC) that achieves a low-frequency SFDR/SNDR of 75.2/62.4 dB and a Nyquist SFDR/SNDR of 65.4/58.5 dB. A significant power reduction while attaining a bandwidth in excess of 6 GHz and a high spectral purity are enabled by: 1) an on-chip terminated very fast settling buffer-less input front end; 2) an on-chip clock chain with as low as 11-fs added jitter; 3) an asynchronous three-stage pipelined-successive approximation register (SAR) sub-ADC; and 4) on-chip co-designed analog–digital calibrations deal with sub-ADC and time-interleaving (TI) artifacts to achieve the desired spectral performance levels. The 28-nm bulk CMOS prototype chip occupies a total area of 4.56 mm<sup>2</sup> with a core area of 1.76 mm<sup>2</sup> and consumes 158.6 mW from a 1-V supply, leading to the Nyquist figure of merits of Schreier (FoM<sub>S</sub>) and Walden (FoM<sub>W</sub>) of 160.5 dB and 46.1 fJ/conversion step, respectively.

[1]  Michiel S. J. Steyaert,et al.  A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS , 2018, IEEE Journal of Solid-State Circuits.

[2]  Qicheng Yu,et al.  A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[3]  Tai-Cheng Lee,et al.  A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration , 2016, 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

[4]  Claudio Nani,et al.  A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[5]  Jon Guerber,et al.  Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .

[6]  Christian Vogel,et al.  The impact of combined channel mismatch effects in time-interleaved ADCs , 2005, IEEE Transactions on Instrumentation and Measurement.

[7]  Jan Craninckx,et al.  A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS , 2012, IEEE Journal of Solid-State Circuits.

[8]  Gabriele Manganaro,et al.  A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology , 2017, IEEE Journal of Solid-State Circuits.

[9]  Borivoje Nikolic,et al.  A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[10]  Jae-Won Nam,et al.  A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation , 2018, IEEE Journal of Solid-State Circuits.

[11]  Akira Matsuzawa,et al.  A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[12]  Michael P. Flynn,et al.  A SAR-Assisted Two-Stage Pipeline ADC , 2011, IEEE Journal of Solid-State Circuits.

[13]  Matthew Martin,et al.  A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[14]  S. P. Astgimath.  A low noise, low power dynamic amplifier with common mode detect and a low power, low noise comparator for pipelined SAR-ADC , 2012 .

[15]  Hae-Seung Lee,et al.  A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration , 2014, IEEE Journal of Solid-State Circuits.

[16]  K. Lee.  Low-destortion switched-capacitor filter design techniques , 1985 .

[17]  Behzad Razavi,et al.  The StrongARM Latch [A Circuit for All Seasons] , 2015, IEEE Solid-State Circuits Magazine.

[18]  Aaron Buchwald.  High-speed time interleaved ADCs , 2016, IEEE Communications Magazine.

[19]  B. Verbruggen,et al.  A 13 bit 5 GS / s ADC with time-interleaved chopping calibration in 16 nm FinFET , 2018 .

[20]  Han Yan,et al.  A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.