Apparatus for the tolerant cache controller and method thereof

The cache control apparatus and method of operation having a fail-safe function is provided. Cache control unit having a fail-safe feature according to one aspect of the present invention for storing and generating a first data and the first parity bit (Parity bit) corresponding to the first data for one particular address read from the main memory, cache (cache) memory, and the second data for said specified address, and the second the shadow cache for storing to generate a second parity bit corresponding to the data (shadow cache) memory, and reading data for the specified address from the processor Upon receiving the request to perform the cache memory and a parity check on the data and parity bits of the specified address is stored in at least one memory of the shadow cache memory (parity check), and the parity check result, stored in the error-free memory and a fault detector to pass data to the processor.