Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations
暂无分享,去创建一个
Tien-Fu Chen | Wei-Chung Cheng | Jinn-Shyan Wang | Tay-Jyi Lin | Pei-Yao Chang | Po-Hao Wang | Yung-Hui Yu | Tang-Chieh Kao | Chi-Lun Tsai | Tien-Fu Chen | Jinn-Shyan Wang | W. Cheng | Chi-Lun Tsai | Tay-Jyi Lin | Po-Hao Wang | Yung-Hui Yu | T. Kao | Pei-Yao Chang
[1] Kaushik Roy,et al. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Reinhold Weicker,et al. Dhrystone: a synthetic systems programming benchmark , 1984, CACM.
[3] Wei Wu,et al. Energy-efficient cache design using variable-strength error-correcting codes , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[4] Daniel J. Costello,et al. Error Control Coding, Second Edition , 2004 .
[5] D. C. Bossen,et al. Orthogonal latin square codes , 1970 .
[6] C.H. Kim,et al. A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode , 2008, IEEE Journal of Solid-State Circuits.
[7] Richard W. Hamming,et al. Error detecting and error correcting codes , 1950 .
[8] Anna W. Topol,et al. Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
[9] A.P. Chandrakasan,et al. A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.
[10] David R. Kaeli,et al. Exploiting temporal locality in drowsy cache policies , 2005, CF '05.
[11] Chin-Long Chen,et al. Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..
[12] Trevor Mudge,et al. MiBench: A free, commercially representative embedded benchmark suite , 2001 .
[13] Abdallah Tubaishat,et al. New hardware architecture for bit-counting , 2006 .
[14] Dwijendra K. Ray-Chaudhuri,et al. Binary mixture flow with free energy lattice Boltzmann methods , 2022, arXiv.org.
[15] Todd M. Austin,et al. SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.
[16] Wei Wu,et al. Improving cache lifetime reliability at ultra-low voltages , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).