On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS’89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

[1]  Mark Mohammad Tehranipoor,et al.  A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Teresa L. McLaurin,et al.  The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Jacob A. Abraham,et al.  On-chip Programmable Capture for Accurate Path Delay Test and Characterization , 2008, 2008 IEEE International Test Conference.

[4]  Richard Putman,et al.  Enhanced timing-based transition delay testing for small delay defects , 2006, 24th IEEE VLSI Test Symposium.

[5]  Irith Pomeranz,et al.  On generating high quality tests for transition faults , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[6]  Ananta K. Majhi,et al.  On hazard-free patterns for fine-delay fault testing , 2004 .

[7]  Chen Wang,et al.  Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects , 2006, 2006 15th Asian Test Symposium.

[8]  Phil Nigh,et al.  Test method evaluation experiments and data , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  Songwei Pei,et al.  An on-chip clock generation scheme for faster-than-at-speed delay testing , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Jing Wang,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004 .

[11]  Toshiyuki Maeda,et al.  Invisible delay quality - SDQM model lights up what could not be seen , 2005, IEEE International Conference on Test, 2005..

[12]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Grading and Pattern Selection for Small-Delay Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).