Leakage power optimization for clock network using dual-Vth technology

Leakage power soars quickly as VLSI technology advance and supply voltage scaling, in the near future, it will exceed the dynamic power to become the main contributor of power dissipation. Previous methods on leakage power minimization always notice the negative effect of increasing the gate's threshold voltage Vth and the power reduction is obtained based on power and speed (or performance) tradeoff. However, increasing the gate's Vth could be used to adjust the subtrees' imbalance for a clock tree. In this paper, for a gated clock tree, we analyze the bottom up merging segment generation process and conclude the conditions for increasing the gate's Vth. Our idea is trying to assign high Vth to the gates without total wirelength and performance overheads, and in some cases, it could even be used to get more balanced subtrees. Experimental results on a set of ISCAS89 benchmark circuits demonstrate that our algorithm could assign more than half of the gates with high Vth, the resultant leakage power reduction is more than 43% without any total wirelength and delay penalties.

[1]  Tadahiro Kuroda.  Low-power, high-speed CMOS VLSI design , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Tadahiro Kuroda,et al.  Utilizing surplus timing for power reduction , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[3]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[4]  Himanshu Kaul,et al.  Future performance challenges in nanometer design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  M.A. Bayoumi,et al.  Leakage sources and possible solutions in nanometer CMOS technologies , 2005, IEEE Circuits and Systems Magazine.

[6]  A. Chatterjee,et al.  Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[7]  Jan-Ming Ho,et al.  Zero skew clock routing with minimum wirelength , 1992 .

[8]  James Kao,et al.  Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.

[9]  Dennis Sylvester,et al.  Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Dennis Sylvester,et al.  Pushing ASIC performance in a power envelope , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[11]  David Blaauw,et al.  Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Yici Cai,et al.  Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[13]  Sung Kyu Lim,et al.  Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization , 2006, ISPD '06.

[14]  D. Sylvester,et al.  Minimizing total power by simultaneous Vdd/Vth assignment , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..