Dynamic circuit restructuring for hierarchical waveform relaxation

A dynamic restructuring method for hierarchical-waveform-relaxation-based circuit analysis is presented. The proposed algorithm is used to dynamically repartition and relevelize the circuit structure during the simulation run in order to achieve faster convergence of the nodal voltage waveforms. Results obtained from analysis of strongly coupled circuits show a factor of 5-10 times speed improvement over flat waveform relaxation (WR)-based circuit simulation and a factor of 2-4 improvement over the static hierarchical WR technique.<<ETX>>