An Efficient Hardware Random Number Generator Based on the MT Method

Mersenne Twister (MT) algorithm is one of the most widely used long-period uniform random number generators. In this paper, we present a novel and efficient hardware architecture for MT method. Our design is implemented on a Xilinx XC6VLX240T-1 FPGA device at 450 MHz. It takes up 0.1% of the device and produces 450 million samples per second, which is 2.25 times faster than a dedicated software version running on a 2.67-GHz Intel core i5 multi-core processor. A dedicated 3R/1W RAM structure is also proposed. It is capable of providing 3 reads and 1 write concurrently in a single clock cycle and is the key component for the entire system to achieve 1 sample-per-cycle throughput. The architecture is also implemented on different FPGA devices. Experimental results show that our generator is superior to those existing architectures reported in the literatures in both performance and hardware complexity. The samples generated by our design are verified via the standard statistics testing suites of Diehard and TestU01.

[1]  Khaled Benkrid,et al.  Mersenne Twister Random Number Generation on FPGA, CPU and GPU , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[2]  Kenji Rikitake.  SFMT pseudo random number generator for Erlang , 2011, Erlang '11.

[3]  Haidong Zhu,et al.  Markov chain Monte Carlo algorithms for CDMA and MIMO communication systems , 2006, IEEE Transactions on Signal Processing.

[4]  Abbes Amira,et al.  High Performance FPGA Implementation of the Mersenne Twister , 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

[5]  Wayne Luk,et al.  A hardware Gaussian noise generator using the Wallace method , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Mutsuo Saito,et al.  An Application of Finite Field: Design and Implementation of 128-bit Instruction-Based Fast Pseudorandom Number Generator , 2007 .

[7]  David Kearney,et al.  An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator , 2006, ERSA.

[8]  James A. Bucklew,et al.  On the Monte Carlo simulation of digital communication systems in Gaussian noise , 2003, IEEE Trans. Commun..

[9]  Takuji Nishimura,et al.  Tables of 64-bit Mersenne twisters , 2000, TOMC.

[10]  David Pellerin,et al.  FPGA-based hardware acceleration of C / C + + based applications-Part 3 , 2022 .

[11]  Jun Igarashi,et al.  Particle Swarm Optimization with SIMD-Oriented Fast Mersenne Twister on the Cell Broadband Engine , 2008, ICONIP.

[12]  K. Ben Letaief,et al.  A quick Monte Carlo technique for simulating direct-detection optical CDMA communications systems , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[13]  Takuji Nishimura,et al.  Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator , 1998, TOMC.

[14]  Pierre L'Ecuyer,et al.  TestU01: A C library for empirical testing of random number generators , 2006, TOMS.

[15]  Craig B. Borkowf,et al.  Random Number Generation and Monte Carlo Methods , 2000, Technometrics.

[16]  Pierre L'Ecuyer,et al.  Fast random number generators based on linear recurrences modulo 2: overview and comparison , 2005, Proceedings of the Winter Simulation Conference, 2005..