SoC integration in deep submicron CMOS

System-on-a-chip (SoC) integration involves a complete system level tradeoff analysis that involves the entire bill of materials, and the architectures used for the communication systems being designed. To realize and optimize SoC requires close collaboration from diverse engineering disciplines, including process integration engineers, circuit engineers, and system engineers to determine the best set of tradeoffs. This synergism will result in finding the most cost effective solution and harness the strengths of the ultra deep submicron process, producing new architectures which will result in innovative solutions to SoC products.

[1]  K. Muhammad,et al.  A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2]  V. Mayega,et al.  A high efficiency ultra-deep sub-micron DC-DC converter for microprocessor applications , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[3]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4]  Heng-Ming Hsu,et al.  A 0.18 /spl mu/m foundry RF CMOS technology with 70 GHz F/sub t/ for single chip system solutions , 2001, 2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157).

[5]  H. Shichijo,et al.  Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[6]  D.D. Buss.  Technology in the Internet age , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  Khurram Muhammad,et al.  A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[8]  Taylor R. Efland,et al.  High-voltage drain extended MOS transistors for 0.18-/spl mu/m logic CMOS process , 2001 .

[9]  D. Leipold,et al.  SOC CMOS technology for personal Internet products , 2003 .

[10]  D. Buss.  Device issues in the integration of analog/RF functions in deep submicron digital CMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).