Delay fault test generation for scan/hold circuits using Boolean expressions

A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated for each fault. These constraints are then manipulated to obtain robust tests, if they exist; otherwise, nonrobust tests are obtained from the constraint functions, if they exist. An implementation of this technique was used to analyze delay fault testability of several ISCAS '89 benchmark circuits.<<ETX>>

[1]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[2]  E BryantRandal.  Graph-Based Algorithms for Boolean Function Manipulation , 1986 .

[3]  Ted Stanion,et al.  TSUNAMI: a path oriented scheme for algebraic test generation , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[4]  Kurt Keutzer,et al.  Robust delay-fault test generation and synthesis for testability under a standard scan design methodology , 1991, 28th ACM/IEEE Design Automation Conference.

[5]  M. Ray Mercer,et al.  A method of delay fault test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[6]  C. Y. Lee.  Representation of switching circuits by binary-decision programs , 1959 .

[7]  Yashwant K. Malaiya,et al.  Modeling and Testing for Timing Faults in Synchronous Sequential Circuits , 1984, IEEE Design & Test of Computers.

[8]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[9]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Vishwani D. Agrawal,et al.  A New Method for Generating Tests for Delay Faults in Non-Scan Circuits , 1992, The Fifth International Conference on VLSI Design.

[11]  Michael H. Schulz,et al.  DYNAMITE: an efficient automatic test pattern generation system for path delay faults , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[13]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[14]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.