An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine

An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algorithm employed in the present work, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. The SVM classifying hardware is composed as an array of Gaussian circuits. Although the system is inherently analog, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. A proof-of concept chip containing 2-class, 2-D, 12-template classifier was designed and fabricated in a 0.18-μm CMOS technology. The experimental results obtained from the fabricated chips are presented and compared with theoretical calculation results. It can classify 8.7 x 105 vectors per second and the average power dissipation was 220 μW. The learning capability was tested using eight fabricated chips and the variability among these chips were evaluated. Successful operation of the chips was confirmed by measurement results, which demonstrates that on-chip-learning can compensate for analog imperfections.

[1]  Paul E. Hasler,et al.  Analog VLSI implementation of support vector machine learning and classification , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[2]  Tadashi Shibata,et al.  An on-chip-trainable Gaussian-kernel analog support vector machine , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[3]  Gert Cauwenberghs,et al.  Kerneltron: Support Vector 'Machine' in Silicon , 2002, SVM.

[4]  Vladimir N. Vapnik,et al.  The Nature of Statistical Learning Theory , 2000, Statistics for Engineering and Information Science.

[5]  Bernhard Schölkopf,et al.  Comparing support vector machines with Gaussian kernels to radial basis function classifiers , 1997, IEEE Trans. Signal Process..

[6]  Nello Cristianini,et al.  An Introduction to Support Vector Machines and Other Kernel-based Learning Methods , 2000 .

[7]  Tobi Delbriick.  "Bump" Circuits for Computing Similarity and Dissimilarity of Analog Voltages , 1991 .

[8]  Davide Anguita,et al.  Learning algorithm for nonlinear support vector machines suited for digital VLSI , 1999 .

[9]  Paul M. Chau,et al.  A radial basis function neurocomputer implemented with analog VLSI circuits , 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

[10]  Davide Anguita,et al.  Circuital implementation of support vector machines , 1998 .

[11]  Tadashi Shibata,et al.  Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology , 2001, NIPS.

[12]  Davide Anguita,et al.  A digital architecture for support vector machines: theory, algorithm, and FPGA implementation , 2003, IEEE Trans. Neural Networks.

[13]  Elisa Ricci,et al.  Analog neural network for support vector machine learning , 2006, IEEE Transactions on Neural Networks.

[14]  Jun Wang,et al.  A one-layer recurrent neural network for support vector machine learning , 2004, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[15]  Tadashi Shibata,et al.  Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors , 2008 .

[16]  Shengyuan Xu,et al.  Delay-Dependent Exponential Stability for Uncertain Stochastic Hopfield Neural Networks With Time-Varying Delays , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[18]  Luke Theogarajan,et al.  A scalable low voltage analog Gaussian radial basis circuit , 1997 .

[19]  Barrie Gilbert,et al.  A precise four-quadrant multiplier with subnanosecond response , 1968, IEEE Solid-State Circuits Newsletter.

[20]  M. Ogawa,et al.  NMOS-based gaussian-element-matching analog associative memory , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[21]  Gert Cauwenberghs,et al.  Silicon Support Vector Machine with On-Line Learning , 2003, Int. J. Pattern Recognit. Artif. Intell..

[22]  Davide Anguita,et al.  Improved neural network for SVM learning , 2002, IEEE Trans. Neural Networks.

[23]  David V. Anderson,et al.  A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier , 2007, VLSI-SoC.

[24]  Nello Cristianini,et al.  An introduction to Support Vector Machines , 2000 .

[25]  Wei Xing Zheng,et al.  On Global Asymptotic Stability of Cohen–Grossberg Neural Networks With Variable Delays , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  S. Chakrabartty,et al.  Sub-Microwatt Analog VLSI Trainable Pattern Classifier , 2007, IEEE Journal of Solid-State Circuits.