论文信息 - A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.

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[2] Claudio Nani,et al. A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist , 2011, 2011 IEEE International Solid-State Circuits Conference.