论文信息 - Mixed 2-4 state simulation with VCS

Mixed 2-4 state simulation with VCS

To meet the demand for higher performance, today's logic simulators are supporting 2 state simulation. Within Chronologic Simulation's VCS simulation system, we have implemented an elaborate infrastructure to support mixed 2-4 state simulation in Verilog. The paper presents our approach to allow mixed 2-4 state simulation while retaining compliance to Verilog HDL language and its simulation semantics. The key issues that need consideration for mixed 2-4 state simulation are discussed in detail. The results obtained by running VCS regression test suite and OVI regression test suite are summarized.

H. K. Chaudhry | P. Eichenberger | D. R. Chowdhury

[1] Ieee Standards Board. IEEE Standard hardware Description language : based on the Verilog hardware description language , 1996 .