A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2.

[1]  S. Palermo,et al.  High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[2]  James S. Harris,et al.  GaInNAsSb/GaAs vertical cavity surface emitting lasers at 1534 nm , 2006 .

[3]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[4]  David V. Plant,et al.  256-channel bidirectional optical interconnect using VCSELs and photodiodes on CMOS , 2000, International Topical Meeting on Optics in Computing.

[5]  Yi Liang,et al.  A Fully Integrated 4×10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13/spl mu/m CMOS SOI , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Fouad E. Kiamilev,et al.  A source-synchronous double-data-rate parallel optical transceiver IC , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997 .

[8]  David A. B. Miller,et al.  The benefits of ultrashort optical pulses in optically interconnected systems , 2003 .

[9]  A. Emami-Neyestanak,et al.  CMOS transceiver with baud rate clock recovery for optical interconnects , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[10]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[11]  Rainer Michalzik,et al.  Design and analysis of single-mode oxidized VCSELs for high-speed optical interconnects , 1999 .

[12]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[13]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[14]  S. Sidiropoulos,et al.  Improving CDR Performance via Estimation , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[15]  A. Emami-Neyestanak,et al.  A 1.6 Gb/s, 3 mW CMOS receiver for optical communication , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[16]  H. Hatakeyama,et al.  1.1-/spl mu/m-range InGaAs VCSELs for high-speed optical interconnections , 2006, IEEE Photonics Technology Letters.

[17]  A. G. Kuzmenkov,et al.  Vertical-cavity surface-emitting lasers based on submonolayer InGaAs quantum dots , 2006, IEEE Journal of Quantum Electronics.

[18]  Jared Zerbe,et al.  A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  L. Schares,et al.  Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies , 2006, IEEE Journal of Selected Topics in Quantum Electronics.

[20]  Azita Emami-Neyestanak,et al.  A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  Alyssa B. Apsel,et al.  Multichannel ultrathin silicon-on-sapphire optical interconnects , 2003 .

[22]  R. Mooney,et al.  A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[23]  P. Larsson,et al.  A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability , 1999, IEEE J. Solid State Circuits.

[24]  A. Upham,et al.  A high-speed, high-sensitivity silicon lateral trench photodetector , 2002, IEEE Electron Device Letters.

[25]  R. John,et al.  120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station , 2004, Journal of Lightwave Technology.

[26]  Hong Q. Hou,et al.  Production of high-speed oxide-confined VCSEL arrays for datacom applications , 2002, SPIE OPTO.

[27]  David A. B. Miller,et al.  Latency in short pulse based optical interconnects , 2001, LEOS 2001. 14th Annual Meeting of the IEEE Lasers and Electro-Optics Society (Cat. No.01CH37242).

[28]  K.W. Goossen,et al.  Reliability of direct mesa flip-chip bonded VCSELs , 2004, The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004. LEOS 2004..

[29]  Shen-Iuan Liu,et al.  A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[30]  L. Coldren,et al.  Diode Lasers and Photonic Integrated Circuits , 1995 .

[31]  Bruce A. Block,et al.  High-speed CMOS-compatible photodetectors for optical interconnects , 2004, SPIE Optics + Photonics.

[32]  F. Ellinger,et al.  A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects , 2005, IEEE Journal of Solid-State Circuits.

[33]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[34]  K.W. Goossen.  Fitting optical interconnects to an electrical world-packaging and reliability issues of arrayed optoelectronic modules , 2004, The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004. LEOS 2004..

[35]  K. Choquette,et al.  Numerical investigation of self-heating effects of oxide-confined vertical-cavity surface-emitting lasers , 2005, IEEE Journal of Quantum Electronics.

[36]  K. Giboney,et al.  Parallel-optical interconnects >100 gb/s , 2004, Journal of Lightwave Technology.

[37]  V. Gupta,et al.  A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels , 2005, IEEE Journal of Solid-State Circuits.

[38]  William J. Dally,et al.  A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[39]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[40]  Kent D. Choquette,et al.  Two-dimensional 8/spl times/8 photoreceiver array and VCSEL drivers for high-throughput optical data links , 2001 .

[41]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.