An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes
暂无分享,去创建一个
[1] Thomas J. Richardson,et al. Error Floors of LDPC Codes , 2003 .
[2] Achilleas Anastasopoulos,et al. Capacity-Achieving Codes With Bounded Graphical Complexity and Maximum Likelihood Decoding , 2010, IEEE Transactions on Information Theory.
[3] Nenad Miladinovic,et al. Improved bit-flipping decoding of low-density parity-check codes , 2002, IEEE Transactions on Information Theory.
[4] Linhua Zheng,et al. An escaping scheme for gradient descent bit-flipping decoding of LDPC codes , 2016, 2016 9th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI).
[5] Ralf Koetter,et al. Towards Low-Complexity Linear-Programming Decoding , 2006, ArXiv.
[6] Fakhreddine Ghaffari,et al. Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.
[7] Emmanuel Boutillon,et al. Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes , 2014, IEEE Transactions on Communications.
[8] Fakhreddine Ghaffari,et al. Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.
[9] T. Wadayama,et al. Gradient descent bit flipping algorithms for decoding LDPC codes , 2008, ISITA 2008.
[10] Bane V. Vasic,et al. Fault-Tolerant Probabilistic Gradient-Descent Bit Flipping Decoder , 2014, IEEE Communications Letters.
[11] Yeong-Luh Ueng,et al. A modified gradient descent bit flipping decoding scheme for LDPC codes , 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).
[12] David Declercq,et al. Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).
[13] Ajay Dholakia,et al. Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.
[14] David Declercq,et al. Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] David Declercq,et al. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units , 2016, 2016 Euromicro Conference on Digital System Design (DSD).
[16] Zhongfeng Wang,et al. An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.
[17] Shu Lin,et al. Low-density parity-check codes based on finite geometries: A rediscovery and new results , 2001, IEEE Trans. Inf. Theory.
[18] Jinghu Chen,et al. Near optimum universal belief propagation based decoding of low-density parity check codes , 2002, IEEE Trans. Commun..
[19] Fakhreddine Ghaffari,et al. A novel high-throughput, low-complexity bit-flipping decoder for LDPC codes , 2017, 2017 International Conference on Advanced Technologies for Communications (ATC).
[20] Bane V. Vasic,et al. Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).
[21] Fakhreddine Ghaffari,et al. A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.
[22] Shahram Yousefi,et al. Trapping Sets of Fountain Codes , 2010, IEEE Communications Letters.
[23] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.