A 128 Mb early prototype for gigascale single-electron memories

A 128Mb single-electron memory targets minimum-bit-cost technology. The cell has a double stacked structure, in which two cells are integrated in an ideal contact area, 4F/sup 2/. The cell-to-cell characteristics variations, the main difficulty in large scale integration, are compensated with the dummy-cell-referenced verified read/write.

[1]  Kazuo Yano,et al.  Room-temperature single-electron memory , 1994 .

[2]  Kazuo Yano,et al.  Impact of Coulomb blockade on low-charge limit of memory device , 1995, Proceedings of International Electron Devices Meeting.

[3]  Kazuo Yano,et al.  A room-temperature single-electron memory device using fine-grain polycrystalline silicon , 1993, Proceedings of IEEE International Electron Devices Meeting.

[4]  T. Matano,et al.  A 4-level storage 4 Gb DRAM , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  K. Yano,et al.  Single-electron-memory integrated circuit for giga-to-tera bit storage , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  T. Sano,et al.  Verify: key to the stable single-electron-memory operation , 1997, International Electron Devices Meeting. IEDM Technical Digest.