FPGA Implementation of a Prototype WDM On-Line Scheduler

Message sequencing and channel assignment are two important aspects to consider in optimizing the performance of Wavelength Division Multiplexing (WDM) networks. A scheduling technique, Multiple-Messages-per-Node with Shortest Job First priority (MMN-SJF), has been proposed to tackle these two areas simultaneously and offers a globally optimizing approach to scheduling. In this paper, a reconfigurable testbed consisting of several interconnected FPGAs for analyzing such scheduling algorithms is introduced and in particular, a prototype scheduler is developed to investigate the implementation and hardware complexity associated with MMN-SJF. We find that the MMN-SJF scheduling technique can be implemented cost effectively and with only simple logic blocks.