Is TSV-based 3D integration suitable for inter-die memory repair?

In this paper we address lower level issues related to 3D inter-die memory repair in an attempt to evaluate the actual potential of this approach for current and foreseeable technology developments. We propose several implementation schemes both for inter-die row and column repair and evaluate their impact in terms of area and delay. Our analysis suggests that current state-of-the-art TSV dimensions allow inter-die column repair schemes at the expense of reasonable area overhead. For row repair, however, most memory configurations require TSV dimensions to scale down at least with one order of magnitude in order to make this approach a possible candidate for 3D memory repair. We also performed a theoretical analysis of the implications of the proposed 3D repair schemes on the memory access time, which indicates that no substantial delay overhead is expected and that many delay versus energy consumption tradeoffs are possible.

[1]  Ding-Ming Kwai,et al.  Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond (Invited Paper) , 2009 .

[3]  Yu-Jen Huang,et al.  Yield-enhancement techniques for 3D random access memories , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[4]  J. Cluzel,et al.  Investigation on TSV impact on 65nm CMOS devices and circuits , 2010, 2010 International Electron Devices Meeting.

[5]  Gabriel H. Loh,et al.  3D-Integrated SRAM Components for High-Performance Microprocessors , 2009, IEEE Transactions on Computers.

[6]  Sani R. Nassif.  The light at the end of the CMOS tunnel , 2010, ASAP.

[7]  Tong Zhang,et al.  Architecture design exploration of three-dimensional (3D) integrated DRAM , 2009, 2009 10th International Symposium on Quality Electronic Design.

[8]  Kiamal Z. Pekmestzi,et al.  Efficient Memory Repair Using Cache-Based Redundancy , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Stefan Rusu.  Trends and challenges in VLSI technology scaling towards 100nm , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[10]  Shyue-Kung Lu,et al.  Yield enhancement techniques for 3-dimensional random access memories , 2012, Microelectron. Reliab..

[11]  S. Rusu,et al.  Trends and challenges in VLSI technology scaling towards 100 nm , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[12]  Shyue-Kung Lu,et al.  On test and repair of 3D random access memory , 2012, 17th Asia and South Pacific Design Automation Conference.

[13]  A. Wang,et al.  Through the Looking Glass: Trend Tracking for ISSCC 2012 , 2012, IEEE Solid-State Circuits Magazine.

[14]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond , 2009 .

[15]  Sung Kyu Lim,et al.  Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs , 2010, SLIP '10.

[16]  K.F. Yang,et al.  TSV process optimization for reduced device impact on 28nm CMOS , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[17]  Masashi Horiguchi,et al.  Nanoscale Memory Repair , 2011, Integrated Circuits and Systems.

[18]  Peter Ramm,et al.  Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .

[19]  P. Soussan,et al.  3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[20]  Qiang Xu,et al.  Yield enhancement for 3D-stacked memory by redundancy sharing across dies , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).