Evolving component library for approximate high level synthesis

An approximate computing approach has recently been introduced for high level circuit synthesis (HLS) in order to make good use of approximate circuits at system and block level. It is assumed in HLS algorithms that a component library containing various implementations of elementary circuit components is available. An open problem is how to construct such a component library in the context of approximate computing, where the component's error is a new design variable and hence many compromise implementations exist for a given component. In this paper, we first introduce a multi-objective Cartesian genetic programming method to create a comprehensive component library containing hundreds of Pareto optimal implementations of approximate 8-bit adders and multipliers, where the error, area and delay are simultaneously optimized. Another multi-objective evolutionary algorithm is employed to solve the so called binding problem of HLS, in which suitable approximate components are assigned to nodes of the data flow graph describing a complex digital circuit. Two approaches are then proposed and compared in order to reduce the size of the library of approximate components. It is shown that a random sub-sampling of the component library provides satisfactory results in the context of our study. The proposed methods are evaluated using two benchmark circuits - the reduce (sum) and DCT circuits.

[1]  Sparsh Mittal,et al.  A Survey of Techniques for Approximate Computing , 2016, ACM Comput. Surv..

[2]  Kaushik Roy,et al.  SALSA: Systematic logic synthesis of approximate circuits , 2012, DAC Design Automation Conference 2012.

[3]  Rolf Drechsler,et al.  BDD minimization for approximate computing , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[4]  Sherief Reda,et al.  ABACUS: A technique for automated behavioral synthesis of approximate computing circuits , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Radek Hrbacek,et al.  Parallel Multi-Objective Evolutionary Design of Approximate Circuits , 2015, GECCO.

[6]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[7]  Lukás Sekanina,et al.  Evolutionary design of complex approximate combinational circuits , 2015, Genetic Programming and Evolvable Machines.

[8]  Yu Ting Chen,et al.  A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Mohammadreza Razzazi,et al.  An Exact Algorithm for the Multiple-Choice Multidimensional Knapsack Based on the Core , 2008, CSICC.

[10]  Wei Luo,et al.  Joint precision optimization and high level synthesis for approximate computing , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Andrew M. Tyrrell,et al.  Use of a multi-objective fitness function to improve cartesian genetic programming circuits , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

[12]  Lara Dolecek,et al.  Underdesigned and Opportunistic Computing in Presence of Hardware Variability , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Marco Platzner,et al.  A novel hybrid evolutionary strategy and its periodization with multi-objective genetic optimizers , 2010, IEEE Congress on Evolutionary Computation.

[14]  Zdenek Vasícek,et al.  Automatic design of approximate circuits by means of multi-objective evolutionary algorithms , 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

[15]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[16]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[17]  Kaushik Roy,et al.  Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Lukás Sekanina,et al.  Evolutionary Approach to Approximate Digital Circuits Design , 2015, IEEE Transactions on Evolutionary Computation.

[19]  Y. Arai,et al.  A Fast DCT-SQ Scheme for Images , 1988 .