Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree

In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip spatial variations recovery at extremely low measurement cost. Applying this method, HMT is introduced to set up a statistical model for coefficients after exploring the underlying correlated representation of the spatial variation in the frequency domain. Accordingly, two key inherent properties of the modeling coefficients, i.e., correlations and sparse presentations in the frequency domain, can be captured exactly and the modeling accuracy can be improved evidently. Then, maximum-a-posteriori estimation is applied to formulate the original problem as a convex optimization that could be solved efficiently and robustly. Numerical results based on industrial data demonstrate that the proposed method can achieve superior accuracy over other existing approaches including orthogonal matching pursuit, l1-norm regularization, and reweighted l1-norm regularization.

[1]  Rob A. Rutenbar,et al.  Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Ashish Kumar Singh,et al.  Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization , 2006, ICCAD.

[3]  Massimo Fornasier,et al.  Compressive Sensing , 2015, Handbook of Mathematical Methods in Imaging.

[4]  Rob A. Rutenbar,et al.  Automatic clustering of wafer spatial signatures , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  M. Orshansky,et al.  Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[6]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[7]  Sani R. Nassif,et al.  Analyzing the impact of process variations on parametric measurements: Novel models and applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Yiorgos Makris,et al.  Spatial correlation modeling for probe test cost reduction in RF devices , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Stephen P. Boyd,et al.  Enhancing Sparsity by Reweighted ℓ1 Minimization , 2007, 0711.1612.

[10]  E.J. Candes.  Compressive Sampling , 2022 .

[11]  Andrzej J. Strojwas,et al.  Correlation-aware statistical timing analysis with non-Gaussian delay distributions , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Rob A. Rutenbar,et al.  Toward efficient spatial variation decomposition via sparse regression , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  R.G. Baraniuk,et al.  Compressive Sensing [Lecture Notes] , 2007, IEEE Signal Processing Magazine.

[14]  Yiorgos Makris,et al.  On combining alternate test with spatial correlation modeling in analog/RF ICs , 2013, 2013 18th IEEE European Test Symposium (ETS).

[15]  Rob A. Rutenbar,et al.  Bayesian Virtual Probe: Minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference , 2010, Design Automation Conference.

[16]  Sachin S. Sapatnekar,et al.  Statistical timing analysis under spatial correlations , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  D. Sylvester,et al.  A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[18]  S. Frick,et al.  Compressed Sensing , 2014, Computer Vision, A Reference Guide.

[19]  Radford M. Neal.  Pattern Recognition and Machine Learning , 2007, Technometrics.

[20]  Stephen J. Wright,et al.  Computational Methods for Sparse Solution of Linear Inverse Problems , 2010, Proceedings of the IEEE.

[21]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[22]  Joel A. Tropp,et al.  Signal Recovery From Random Measurements Via Orthogonal Matching Pursuit , 2007, IEEE Transactions on Information Theory.

[23]  Rob A. Rutenbar,et al.  Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[24]  William A. Pearlman,et al.  A new, fast, and efficient image codec based on set partitioning in hierarchical trees , 1996, IEEE Trans. Circuits Syst. Video Technol..

[25]  A. Arulmurugan,et al.  Survey of low power testing of VLSI circuits , 2012, 2012 International Conference on Computer Communication and Informatics.

[26]  Rob A. Rutenbar,et al.  Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Sherief Reda,et al.  Thermal monitoring of real processors: Techniques for sensor allocation and full characterization , 2010, Design Automation Conference.

[28]  Wen-Shyong Hsieh,et al.  Digital watermarking using zerotree of DCT , 2000, IEEE Trans. Consumer Electron..

[29]  Farid N. Najm,et al.  Statistical timing analysis with two-sided constraints , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[30]  Kenneth M. Butler,et al.  Test cost reduction through performance prediction using virtual probe , 2011, 2011 IEEE International Test Conference.

[31]  Nick G. Kingsbury,et al.  Hidden Markov tree modeling of complex wavelet transforms , 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

[32]  Yiorgos Makris,et al.  Spatial estimation of wafer measurement parameters using Gaussian process models , 2012, 2012 IEEE International Test Conference.

[33]  Lawrence R. Rabiner,et al.  A tutorial on hidden Markov models and selected applications in speech recognition , 1989, Proc. IEEE.

[34]  Sachin S. Sapatnekar,et al.  Synthesizing a representative critical path for post-silicon delay prediction , 2009, ISPD '09.

[35]  K. Ravindran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[37]  W. Campbell,et al.  THE UNIVERSITY OF TEXAS AT DALLAS , 2004 .

[38]  M.B. Ketchen,et al.  Ring oscillators for CMOS process tuning and variability control , 2006, IEEE Transactions on Semiconductor Manufacturing.

[39]  Jerome M. Shapiro,et al.  Embedded image coding using zerotrees of wavelet coefficients , 1993, IEEE Trans. Signal Process..

[40]  Michael T. Orchard,et al.  A comparative study of DCT- and wavelet-based image coding , 1999, IEEE Trans. Circuits Syst. Video Technol..

[41]  Jae S. Lim,et al.  Efficient coding of DCT coefficients by joint position-dependent encoding , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[42]  Z. Xiong,et al.  A DCT-based embedded image coder , 1996, IEEE Signal Processing Letters.

[43]  Rob A. Rutenbar,et al.  Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[44]  Robert D. Nowak,et al.  Wavelet-based statistical signal processing using hidden Markov models , 1998, IEEE Trans. Signal Process..

[45]  Yiorgos Makris,et al.  Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[46]  Kenneth M. Butler,et al.  A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[47]  Emmanuel J. Candès,et al.  Decoding by linear programming , 2005, IEEE Transactions on Information Theory.

[48]  William R. Mann,et al.  The leading edge of production wafer probe test technology , 2004, 2004 International Conferce on Test.