Minimization of average path length in BDDs by variable reordering

Abstract : Minimizing the Average Path Length (APL) in a BDD reduces the time needed to evaluate Boolean functions represented by BDDs. This paper describes an efficient heuristic APL minimization procedure based on BDD variable reordering. The reordering algorithm is similar to classical variable sifting with the cost function equal to the APL rather than the number of BDD nodes. The main contribution of our paper is a fast way of updating the APL during the swap of two adjacent variables. Experimental results show that the proposed algorithm effectively minimizes the APL of large MCNC benchmark functions, achieving reductions of up to 47%. For some benchmarks, minimizing APL also reduces the BDD node count.

[1]  Rolf Drechsler,et al.  Using lower bounds during dynamic BDD minimization , 1999, DAC '99.

[2]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, DAC.

[3]  R. Drechsler,et al.  Transformations amongst the Walsh, Haar, Arithmetic and Reed-Muller Spectral Domains , 2001 .

[4]  Richard Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Tsutomu Sasao,et al.  A hardware simulation engine based on decision diagrams , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[7]  Tsutomu Sasao,et al.  Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams , 2002 .

[8]  TingTing Hwang,et al.  Binary decision diagram with minimum expected path length , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Tsutomu Sasao,et al.  Comparison of Decision Diagrams for Multiple-Output Logic Functions , 2002, IWLS.

[10]  C. K. Chow,et al.  On the characterization of threshold functions , 1961, SWCT.

[11]  Masahiro Fujita,et al.  On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..

[12]  Michael L. Dertouzos,et al.  Threshold Logic: A Synthesis Approach , 1965 .

[13]  Hiroshi Sawada,et al.  Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[14]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .