An Efficient Scan Tree Design for Compact Test Pattern Set

Tree-based scan path architectures have recently been suggested for reducing test application time or test data volume in today's high-density very large scale integrated circuits. However, these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set and therefore may not be suitable for a highly compact test set generated by an efficient automatic test pattern generator tool. Tree-based architectures also suffer from loss of fault coverage while achieving a significant reduction ratio for test time or data. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture based on approximate compatibility. The method is particularly suitable for a highly compact test set having fewer don't cares and low compatibility. Finally, to reduce the volume of scan-out data, test responses shifted out from the leaf nodes of the scan tree are compacted by a space compactor, which is designed specially for the proposed scan tree architecture. The compactor uses an XOR tree, and its overhead is low. The design thus offers a solution to both test data and response compaction. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing test application time significantly without degrading fault coverage.

[1]  Janak H. Patel,et al.  Enhancement of the Illinois scan architecture for use with multiple scan inputs , 2004, IEEE Computer Society Annual Symposium on VLSI.

[2]  Patrick Girard,et al.  An efficient scan tree design for test time reduction , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[3]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[4]  Charles Fleurent,et al.  Genetic and hybrid algorithms for graph coloring , 1996, Ann. Oper. Res..

[5]  Hideo Fujiwara,et al.  Improving test effectiveness of scan-based BIST by scan chain partitioning , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Sandeep K. Gupta,et al.  Designing reconfigurable multiple scan chains for systems-on-chip , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[7]  Kozo Kinoshita,et al.  On configuring scan trees to reduce scan shifts based on a circuit structure , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

[8]  Hailong Cui,et al.  Modeling Fault Coverage of Random Test Patterns , 2003, J. Electron. Test..

[9]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.

[10]  Daniel Brélaz,et al.  New methods to color the vertices of a graph , 1979, CACM.

[11]  Yervant Zorian,et al.  Test requirements for embedded core-based systems and IEEE P1500 , 1997, Proceedings International Test Conference 1997.

[12]  Kohei Miyase,et al.  Optimal scan tree construction with test vector modification for test compression , 2003, 2003 Test Symposium.

[13]  Jia-Guang Sun,et al.  A cost-effective scan architecture for scan testing with non-scan test power and test application cost , 2003, DAC '03.

[14]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Thomas W. Williams,et al.  Design of compactors for signature-analyzers in built-in self-test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Elizabeth M. Rudnick,et al.  A genetic approach to test application time reduction for full scan and partial scan circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.

[17]  Kozo Kinoshita,et al.  Reducing scan shifts using folding scan trees , 2003, 2003 Test Symposium.

[18]  Janak H. Patel,et al.  A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[19]  Hideo Fujiwara,et al.  Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops , 2005, 14th Asian Test Symposium (ATS'05).

[20]  Bashir M. Al-Hashimi,et al.  Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits , 2002, IEEE Trans. Computers.

[21]  Kewal K. Saluja,et al.  An algorithm to reduce test application time in full scan designs , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[22]  Sheng Zhang,et al.  On finding consecutive test vectors in a random sequence for energy-aware BIST design , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[23]  Sudhakar M. Reddy,et al.  Multiple scan tree design with test vector modification , 2004, 13th Asian Test Symposium.