Wire-Streaming Processors on 2-D Nanowire Fabrics

Most of the research in the field of nanoelectronics has been focused on nanodevice and nano-fabrication aspects. By contrast, very little work has been reported on the design or ca- pabilities of circuits and computational architectures that can be built out of nanodevices. A key challenge in any nanoscale system is to preserve the density advantage of the underlying nanodevice. Topological, interconnect, and fault-tolerance constraints can, however, severely impact the effective system-level density that can be achieved. This paper explores designs on silicon nanowire based 2-D computing fabrics that, while also programmable and hierarchical, are more tuned towards an application domain than PLA style approaches. Our goal is to achieve denser designs with better fabric utilization and efficient cascading of circuits. We call these designs NASICs: Nanoscale Application- Specific Integrated Circuits . In this paper we demonstrate possible NASIC optimizations, within the constraints of sub-lithographic fabrication, that improve fabric utilization. Finally, we design and evaluate a simple nanoscale stream processor and compare its density to an equivalent synthesized CMOS implementation scaled to 30-nm CMOS. Our results show that, despite this small design being dominated by microwires, a 12.5X density advantage can be achieved on a defect-free fabric. We estimate that larger NASIC designs could be 100X denser compared to CMOS before fault tolerance techniques are applied.