Cryogenic Support Circuits and Systems for Silicon Quantum Computers

Scaled-up silicon quantum computers show great potential for being manufacturable in processes similar to modern ultra-deep sub-micron integrated circuit CMOS manufacturing processes. The operation of quantum computing cores require extensive support functions in terms of biasing, controlling and quantum state readout; functions that are implemented using classical electronic circuits. Since silicon quantum computer cores need to operate at deep cryogenic temperatures, therefore, the electronic support functions for scale-up quantum cores need – at least to some extent – to also operate at deep cryogenic temperatures. In this paper we discuss challenges associated with designing CMOS integrated support electronics for silicon quantum computer cores operating at cryogenic temperatures below carrier freeze-out. We look at device issues such as cold transistor characteristics and mismatch, circuit design techniques, and systems challenges such as nano-scale to micro-scale fan-out.

[3]  Arnout Beckers,et al.  Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K , 2018, IEEE Journal of the Electron Devices Society.

[4]  T. Lehmann,et al.  Quantum bit controller and observer circuits in SOS-CMOS technology for gigahertz low-temperature operation , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).

[5]  O. Faynot,et al.  First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers , 2016, 2016 IEEE Symposium on VLSI Technology.

[6]  E. Charbon,et al.  Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures , 2018, IEEE Journal of the Electron Devices Society.

[7]  Torsten Lehmann,et al.  A Self-Calibrated Cryogenic Current Cell for 4.2 K Current Steering D/A Converters , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  P. Barthelemy,et al.  Long-distance coherent coupling in a quantum dot array. , 2013, Nature nanotechnology.

[9]  M. Veldhorst,et al.  Silicon CMOS architecture for a spin-based quantum computer , 2016, Nature Communications.

[10]  Torsten Lehmann,et al.  Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective , 2014 .

[11]  J. P. Dehollain,et al.  A two-qubit logic gate in silicon , 2014, Nature.

[12]  Edoardo Charbon,et al.  Cryo-CMOS Circuits and Systems for Quantum Computing Applications , 2018, IEEE Journal of Solid-State Circuits.

[13]  M. Peckerar,et al.  Compact modeling of 0.35µm SOI CMOS technology node for 4K DC operation using Verilog-A , 2010 .

[14]  J. Mazurier,et al.  14nm FDSOI technology for high speed and energy efficient applications , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[15]  Craig T. Jin,et al.  Impact of Series Resistance on Bulk CMOS Current Matching Over the 5–300K Temperature Range , 2017, IEEE Electron Device Letters.

[16]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[17]  C. Enz,et al.  Characterization and Modeling of 28 nm Bulk CMOS Technology down to 4 . 2 K ( Invited Paper ) , 2018 .

[18]  Mostafa Rahimi Azghadi,et al.  An enhanced MOSFET threshold voltage model for the 6-300 K temperature range , 2017, Microelectron. Reliab..

[19]  Arnout Beckers,et al.  Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing , 2018, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[20]  T. Lehmann,et al.  Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout , 2010, IEEE Transactions on Electron Devices.

[21]  Torsten Lehmann,et al.  Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  H. Lu,et al.  Cryogenic Control Architecture for Large-Scale Quantum Computing , 2014, 1409.2202.

[23]  M. Vinet,et al.  28nm Fully-depleted SOI technology: Cryogenic control electronics for quantum computing , 2017, 2017 Silicon Nanoelectronics Workshop (SNW).

[24]  Michelle Y. Simmons,et al.  Silicon quantum electronics , 2012, 1206.5202.

[25]  Edoardo Charbon,et al.  Characterization and Model Validation of Mismatch in Nanometer CMOS at Cryogenic Temperatures , 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

[26]  Edoardo Charbon,et al.  A reconfigurable cryogenic platform for the classical control of quantum processors. , 2016, The Review of scientific instruments.

[27]  S. Debnath,et al.  Demonstration of a small programmable quantum computer with atomic qubits , 2016, Nature.