MACACO: Modeling and analysis of circuits for approximate computing
暂无分享,去创建一个
Kaushik Roy | Amit Agarwal | Anand Raghunathan | Rangharajan Venkatesan | Rangharajan Venkatesan | A. Agarwal | K. Roy | A. Raghunathan
[1] Naresh R. Shanbhag,et al. Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[2] Kartik Mohanram,et al. Approximate logic circuits for low overhead, non-intrusive concurrent error detection , 2008, 2008 Design, Automation and Test in Europe.
[3] Kaushik Roy,et al. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency , 2010, Design Automation Conference.
[4] Christian Stangier,et al. A Partitioning Methodology for BDD-Based Verification , 2004, FMCAD.
[5] John Sartori,et al. Slack redistribution for graceful degradation under voltage overscaling , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[6] Subhasish Mitra,et al. ERSA: Error Resilient System Architecture for probabilistic applications , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[7] Randal E. Bryant,et al. Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.
[8] Kaushik Roy,et al. Design of voltage-scalable meta-functions for approximate computing , 2011, 2011 Design, Automation & Test in Europe.
[9] Douglas L. Jones,et al. Stochastic computation , 2010, Design Automation Conference.
[10] Kaushik Roy,et al. IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.
[11] Deming Chen,et al. DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[12] Puneet Gupta,et al. Trading Accuracy for Power with an Underdesigned Multiplier Architecture , 2011, 2011 24th Internatioal Conference on VLSI Design.
[13] Paolo Ienne,et al. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.
[14] Melvin A. Breuer,et al. Hardware that produces bounded rather than exact results , 2010, Design Automation Conference.
[15] Zhi-Hui Kong,et al. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Sandeep K. Gupta,et al. Approximate logic synthesis for error tolerant applications , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[17] Naresh R. Shanbhag,et al. Energy-efficient signal processing via algorithmic noise-tolerance , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[18] John Lach,et al. Exploring the fidelity-efficiency design space using imprecise arithmetic , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).
[19] Karem A. Sakallah,et al. ZBDD-Based Backtrack Search SAT Solver , 2002, IWLS.
[20] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[21] Anand Raghunathan,et al. Best-effort computing: Re-thinking parallel software and hardware , 2010, Design Automation Conference.
[22] Alexander Saldanha,et al. Is redundancy necessary to reduce delay , 1990, DAC '90.
[23] Krishna V. Palem,et al. Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices , 2003, CASES '03.