Rectification Method for

Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for look-up table type FPGA’s. Instead of changing the netlist of a circuit, we only modify functionality realized by look-up tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques.

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