Carrier Transport Characteristics of Sub-30 nm Strained N-Channel FinFETs Featuring Silicon-Carbon Source/Drain Regions and Methods for Further Performance Enhancement

We report performance optimization techniques for FinFETs with Si _0.99C_0.01 source and drain (S/D) regions and sub-30 nm gate lengths. By scaling up the Si_0.99C_0.01 stressor thickness, a ~9% I_Dsat enhancement can be obtained. A further 16% I_Dsat enhancement can be achieved with the adoption of slim spacers. Carrier backscattering study was performed to clarify the carrier transport characteristics such as ballistic efficiency and carrier source injection, showing consistency with observed I_Dsat enhancement