A fully pipelined, 700 MBytes/s DES encryption core

Fully-pipelined, 56-bit DES de/encryption and authentication at memory-bus bandwidths is now feasible. We describe a custom, 7 square mm, 120 mW core in 4-metal 0.35 /spl mu/m CMOS. Performance allows on-the-fly encryption of 64-bit, 66 MHz PCI traffic, and hence typical network traffic. FPGA, synthesized, and 3-metal versions are compared.