Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation

The paper proposes a low density parity check (LDPC) code design system to facilitate the design of communication systems using LDPC codes for error correction. The proposed LDPC code design system has three advantages (utilization of MOGA to search codes, speed enhancement achieved through parallelization and FPGAs, and employment of more precise simulation models) and solves problems encountered when LDPC codes are used in practical applications. Preliminary evaluation results for the proposed system are presented, which demonstrate that the system can function successfully.