Feedforward architectures for parallel viterbi decoding

[1]  Gerhard Fettweis,et al.  Minimized method Viterbi decoding: 600 Mbit/s per chip , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[2]  Gerhard Fettweis,et al.  High-Rate Viterbi Processor: A Systolic Array Solution , 1990, IEEE J. Sel. Areas Commun..

[3]  Gerhard Fettweis,et al.  Cascaded feedforward architectures for parallel Viterbi decoding , 1990, IEEE International Symposium on Circuits and Systems.

[4]  Gerhard Fettweis,et al.  Algorithm transformations for unlimited parallelism , 1990, IEEE International Symposium on Circuits and Systems.

[5]  H. Meyr,et al.  A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[6]  Gerhard Fettweis,et al.  On the interaction between DSP-algorithms and VLSI-architecture , 1990, International Zurich Seminar on Digital Communications, Electronic Circuits and Systems for Communications..

[7]  Gerhard Fettweis,et al.  Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck , 1989, IEEE Trans. Commun..

[8]  David G. Messerschmitt,et al.  Algorithms and architectures for concurrent Viterbi decoding , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[9]  John M. Cioffi,et al.  A block processing method for designing high-speed Viterbi detectors , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[10]  Keshab K. Parhi,et al.  Look-ahead in dynamic programming and quantizer loops , 1989, IEEE International Symposium on Circuits and Systems,.

[11]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[12]  Lothar Thiele,et al.  On the hierarchical design of VLSI processor arrays , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[13]  Thomas Kailath,et al.  Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[14]  Christian Müller-Schloer,et al.  Design of VLSI circuits - based on Venus , 1987 .

[15]  R. J. F. Fang,et al.  A coded 8-PSK system for 140 Mb/s information rate transmission over 80 MHz non-linear transponders† , 1986 .

[16]  Heinrich Meyr,et al.  Rotationally invariant trellis codes for mPSK modulation , 1987 .

[17]  Hans Burkhardt,et al.  Contributions to the application of the Viterbi algorithm , 1985, IEEE Trans. Inf. Theory.

[18]  Jeffrey D Ullma.  Computational Aspects of VLSI , 1984 .

[19]  J. S. Snyder,et al.  High-speed Viterbi decoding of high-rate codes , 1983 .

[20]  C. Barnes,et al.  Block-shift invariance and block implementation of discrete-time filters , 1980 .

[21]  Andrew J. Viterbi,et al.  Principles of Digital Communication and Coding , 1979 .

[22]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[23]  J. Omura,et al.  On the Viterbi decoding algorithm , 1969, IEEE Trans. Inf. Theory.

[24]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.

[25]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[26]  Stuart E. Dreyfus,et al.  Applied Dynamic Programming , 1965 .