Equalization in high-speed communication systems

The article first discusses the major non-ideal issues of low-cost transmission media for over Gbps data transmissions - the frequency dispersion loss and channel noise. The former causes ISI in received signal, which presents difficulty for clock and data recovery at high frequencies and results higher BER. The latter further degrades the received signal quality and further limits the data transmission rate and transmission distance. Then, two equalization approaches - transmitter pre-emphasis and receiver equalization, are reviewed, in addition to various adaptation criteria and algorithms.

[1]  Shlomo Shamai,et al.  On the capacity of a twisted-wire pair: Gaussian model , 1990, IEEE Trans. Commun..

[2]  Jin Liu,et al.  Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  A.A. Abidi,et al.  A discrete-time analog signal processor for disk read channels , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  R. Dakshinamurthy,et al.  A 200 Mb/s analog DFE read channel , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5]  P. R. Gray,et al.  Parallelism in analog and digital PRML magnetic disk read channel equalizers , 1995 .

[6]  H. Tamura,et al.  Partial response detection technique for driver power reduction in high speed memory-to-processor communications , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[7]  C.M. Melas,et al.  Adaptive equalization in magnetic-disk storage channels , 1990, IEEE Communications Magazine.

[8]  David A. Johns,et al.  Comparison of DC offset effects in four LMS adaptive algorithms , 1995 .

[9]  Jacques C. Rudell,et al.  A 50 MHz eight-tap adaptive equalizer for partial-response channels , 1995 .

[10]  Randall L. Geiger,et al.  A 2V low–power CMOS 125Mbaud repeater architecture for UTP5 cables , 2002 .

[11]  Paul J. Hurst,et al.  A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-/spl mu/m CMOS , 1996 .

[12]  William J. Dally,et al.  Digital systems engineering , 1998 .

[13]  T. Lee,et al.  A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter , 1999 .

[14]  Jan W. M. Bergmans,et al.  Digital baseband transmission and recording , 1996 .

[15]  K. Nagaraj,et al.  A high speed, low power PRML read channel device , 1995 .

[16]  Y. Tsividis,et al.  RLC active filters with electronically tunable centre frequency and quality factor , 1994 .

[17]  Jin Liu,et al.  A high speed low-noise equalization technique with improved bit error rate , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[18]  U. Langmann,et al.  A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[19]  A. Rylyakov,et al.  A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[20]  R. R. Spencer,et al.  A low-power 170-MHz discrete-time analog FIR filter , 1998 .

[21]  Rinaldo Castello,et al.  A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo , 1997 .

[22]  Hong-June Park,et al.  A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme , 2002 .

[23]  K. Azadet,et al.  A low power 128-tap digital adaptive equalizer for broadband modems , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[24]  A. Buchwald,et al.  A sampled-data switched-current analog 16-tap FIR filter with digitally programmable coefficients in 0.8 /spl mu/m CMOS , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[25]  Asad A. Abidi,et al.  A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels , 1996 .

[26]  K. Muhammad,et al.  A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels , 2000, IEEE Journal of Solid-State Circuits.

[27]  M.H. Shakiba.  A 2.5 Gb/s adaptive cable equalizer , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[28]  Chung-Yu Wu,et al.  The design of a 3-V 900-MHz CMOS bandpass amplifier , 1997 .

[29]  W.J. Dally,et al.  Transmitter equalization for 4-Gbps signaling , 1997, IEEE Micro.

[30]  Christopher J. Diorio,et al.  A mixed-signal approach to high-performance low-power linear filters , 2001, IEEE J. Solid State Circuits.

[31]  C. Johnson,et al.  Theory and design of adaptive filters , 1987 .

[32]  Paul J. Hurst,et al.  An analog DFE for disk drives using a mixed-signal integrator , 1999 .

[33]  Modeling and Analysis Of Digital Optical Communications Systems , 2003 .

[34]  Z. Ciota,et al.  Analogue realisation of integrated FIR filters , 1996 .

[35]  John Choma,et al.  Stability of a continuous-time state variable filter with op-amp and OTA-C integrators , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[36]  Deog-Kyoon Jeong,et al.  A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[37]  D. J. Allstot,et al.  A 0.5-8.5 GHz fully differential CMOS distributed amplifier , 2002 .

[38]  Thomas Wong,et al.  Fundamentals of distributed amplification , 1993 .

[39]  Z. Czarnul,et al.  MOS transconductors and integrators with high linearity , 1986 .

[40]  G.T. Uehara,et al.  A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 /spl mu/m CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[41]  G. Feygin,et al.  A 160 MHz analog equalizer for magnetic disk read channels , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[42]  R. Mactaggart,et al.  A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[43]  Gu-Yeon Wei,et al.  An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS , 2003 .

[44]  R. Senthinathan,et al.  0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[45]  John G. Proakis,et al.  Digital Communications , 1983 .

[46]  A.J. Baker.  An adaptive cable equalizer for serial digital video rates to 400 Mb/s , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[47]  Muneo Fukaishi,et al.  A 0.13-/spl mu/m CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer , 2003 .

[48]  H. Tamura,et al.  A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[49]  Kenneth W. Martin,et al.  Continuous-time adaptive-analog coaxial cable equalizer in 0.5 /spl mu/m CMOS , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[50]  T. Lee,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[51]  Omid Shoaei,et al.  A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[52]  N.P. Kelly,et al.  A mixed-signal DFE/FFE receiver for 100Base-TX applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[53]  J. N. Babanezhad.  A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[54]  M. Altmann,et al.  A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[55]  E. Burlingame,et al.  An analog CMOS high-speed continuous-time FIR filter , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[56]  Michael P. Flynn,et al.  A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS , 2001 .

[57]  Behzad Razavi,et al.  A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[58]  Howard W. Johnson,et al.  High Speed Signal Propagation: Advanced Black Magic , 2003 .

[59]  Mark I. Montrose,et al.  EMC and the printed circuit board : design, theory, and layout made simple , 1999 .